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    601 altera de1 งานที่พบ, การเสนอราคา USD
    FPGA replacement on Control Board - Prototype Phase หมดเขตแล้ว left

    I'm looking for an individual with expertise in Altium Designer. This project involves replacing an obsolete Xilinx FPGA with an Altera part. The initial project has been done in Altium Designer. ECAD would need to be done in Altium 19.

    $161 (Avg Bid)
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    18 คำเสนอราคา
    Custom FPGA Logic Wizard Needed หมดเขตแล้ว left

    ...freelancer with expertise in FPGA coding to bring a custom logic design project to life in Noida (Delhi/NCR). **Project Objectives:** - Development and implementation of custom logic designs using FPGA. - Ensuring designs are efficient, reliable, and meet project requirements. **Skills and Experience:** - Strong background in FPGA programming and design, with specific experience in either Xilinx, Altera, or Lattice platforms preferred. - Proven ability to develop and optimize custom logic designs. - Excellent problem-solving skills and creativity in designing unique solutions. - Ability to work independently and deliver project milestones on time. **Application Requirements:** - convert LVDS signals to MIPI CSI2. - preferably using Lattice crosslink. This project offers an ex...

    $380 (Avg Bid)
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    FPGA UART Interface Expert หมดเขตแล้ว left

    I'm seeking a talented individual with a strong background in VHDL and FPGA design, specifically with Altera products, who can successfully implement communication interfaces within my project. The ideal candidate will possess a deep understanding of UART protocol and be capable of integrating it with other interfaces. Requirements: - Proficiency in VHDL programming for FPGA - Experience with Altera FPGA design tools - Successful implementation of UART interfaces - Knowledge in LAN and USB communication The scope of the project includes: - Implementing a low-speed UART interface (up to 115200 bps) - Integrating UART with LAN and USB interfaces on the FPGA The right freelancer will have a strong portfolio demonstrating their expertise in FPGA interface design and commu...

    $520 (Avg Bid)
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    20 คำเสนอราคา
    FPGA Function Generator หมดเขตแล้ว left

    I am looking to hire a freelancer to design an FPGA function generator using a Altera MAX 10 FPGA, 10M08SAE144C8G that produces a frequency of 10 MHz and above. The desired waveforms are sine, square, and triangle. This function generator should also have a single channel. If you think you have the skills to help me with this project, feel free to bid on it. Thank you!

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    5 คำเสนอราคา
    c# developer หมดเขตแล้ว left

    Possuo um projetto em c# simples, que realiza algumas ações no computador da pessoa que executa. São elas: - Abre navegador de internet em uma pagina especifica - Abre 20 janelas de CMD com uma mensagem especifica - Altera o papel de parede O executável funciona perfeitamente, mas quando compartilhado com outros usuários, o google chrome está identificando como ameaça e não permite o download. Preciso corrigir isto até amanhã de manha.

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    เร่งด่วน
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    fpga programming หมดเขตแล้ว left

    My project is about FPGA programming for control systems. I'm using the Altera Cyclone V board and the preferred programming language is Verilog. This project requires someone with experience in FPGA programming and the design of embedded systems. The programmer should be able to develop design flows for FPGA devices, debug them and modify existing designs for better performance. The knowledge of hardware description languages such as VHDL and Verilog is crucial, as they will be used for implementation and testing of the designs. Additionally, some knowledge of microcontrollers and communication protocols will be required. The right person for this job should have strong problem-solving skills, excellent coding and debugging capabilities, and a deep understanding of hardware in...

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    um pequeno software em WP หมดเขตแล้ว left

    SISTEMA MANUAL DE CARGOS LANÇAR / CONSULTAR / ALTERAR FORMULÁRIO DE DESCRIÇÃO DE CARGO CONSULTAR SETOR E DEPOIS O CARGO DESEJADO DADOS DO FORMULÁRIO DE DESCRIÇÃO DE CARGOS CARGO CBO DEPTO SETOR Grade Pleno: MISSÃO RESPONSABILIDADES - PELO MENOS 30 LINHAS PARA DESCREVER ESCOLARIDADE EXPERIÊNCIA I...os dados dos colaboradores e aprovar a descrição ou não RH tem acesso o a tudo Administrador tem acesso a tudo seria interessante ter um botão de aprovação para ele apertar e se ainda não apertou ficar com status de em aprovação. Login / Senha com alçadas (3 tipos de alçadas) 1 - só cadastrar ao finalizar não ter poder de alterar nem excl...

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    Help me with altera de0 board หมดเขตแล้ว left

    Project Title: Altera DE0 Board Programming Assistance Description: I am seeking a freelancer who can provide programming assistance for my Altera DE0 board project. I require expertise in VHDL programming language and the ability to modify existing code as well as start from scratch. Skills and Experience: The ideal candidate for this project should have: - Proficiency in VHDL programming language - Experience with Altera DE0 board - Strong troubleshooting and debugging skills - Knowledge of hardware design consultation Specific requirements: - Provide programming assistance for the Altera DE0 board - Modify existing code and develop new code from scratch - Troubleshoot and debug any issues that arise during the programming process - Provide hardware design ...

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    Modificacion de scripts para gsheets. หมดเขตแล้ว left

    Buenas tardes, tengo algunos script a corregir como el que adjuntare, el error en ese script es básicamente un desface que tiene, la función es del script es llenar un formato de citación en ghseets, se encarga de copiar las notas de una hoja a la hoja citación, desde la primer citación a la quinta, lo hace muy bien, después de la quinta citación he agregado una fila en blanco, la cual altera los rangos a la sexta citación y siguientes, pegando los valores una fila mas abajo de donde debería. tambien tengo otros script con algunos detalles, lo podriamos hablar en privado.

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    FPGA interfacing with AFE and sub systems หมดเขตแล้ว left

    Hello,I am looking for devs who has experience and knowledge in FPGA to interface RF AFE chip from analogue device(exact part number via chat) Desired FPGA- xilinx Zynq/ equivalent series, Cyclone/equivalent from altera. The FPGA will be interfaced with the AFE and will act as an DSP. Apart from the AFE the FPGA is expected t be interfaced with: 1) Display module 2) Keypad 3) Memory 4) Microphone 5) ESP32C3 and GNSS module. Additional MCU/processor can be added to reduce the burden on FPGA. It can be decided after discussing. The FPGA will perform the DSP task and will be used to transmit RF waveforms. It will be used to perform frequency hopping and encryption (AES-256/SHA) task for the waveform. More detailed information via chat. Eligibility: The freelancer must have...

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    EE Engineer for the smart bottle หมดเขตแล้ว left

    I am an EE engineer. I have lots of experience designi...Assembly language and C/C++ (both procedural and OOP). *for STM and nrf controllers Mbed OS could be one of the choices for programming the MCU. I have done lots of projects in the field of wireless communication and IoT using different wireless communication protocols like BLE, RF, WiFi (Cloud), etc. In the field of bit streaming, high-speed processing and ML, I am able to program both Xilinx and Altera in VHDL or C/C++ for Microblaze or NIOS II processors. For manufacturing purposes, I can provide component selection and BOM which suits your needs for a durable, efficient, and effective design. ABOUT YOUR PROJECT, I have done lots of similar projects before and can handle your project easily. We may discuss it more over cha...

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    ...developing co-design projects. There are many possible solutions to the design problems depending on the way in which you choose to partition each problem. HW/SW Specs: The target embedded systems platform can be either the AlteraDE0 FPGA platform or the PSOC. Both devices/boards provide the opportunity to implement low-level, interrupt driven, device drivers along with the custom hardware. Altera DE0 Board: This board has a Cyclone III FPGA fitted. This supports a ’soft-core’ processor integrated with custom hardware. Using the Nios2 softcore CPU as a base you will implement a system to control a robot arm. There is the potential to use a small embedded O/S, FreeRTOS, uCLinux, or to write your own scheduler for this solution. PSoC: PSoC is industry&rsqu...

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    Script para automatizar mensagens no whatsapp หมดเขตแล้ว left

    ...EDITADO EM DOIS CAMPOS O MIN E O MAX DEIXA A UNIDADE DE MEDIDA EM SEGUNDOS TER UMA CHECK BOX QUE EU POSSA MARCAR, ONDE QDO MARCADA ELE IGNORA ENVIAR A MSG CASO ESTE CONTATO JA TENHA SIDO CONTATADO, E QUE SE NAO TIVER MARCADA ELE ENVIA A MSG MESMO ASSIM E OUTRA CHECK BOX, ONDE QUANDO MARCADA ELE MARCA AS MSGS DE EMAIL COMO LIDA, CASO ELE TENHA ENVIADO A MSG PARA ELE, E SE NAO MARCADA NAO ALTERA NADA NA MSG DE EMAIL NO SERVIDOR...

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    Postcode Data Sorted – 210323 หมดเขตแล้ว left

    Brief – Postcode Data Sorted – 210323The job is to filter a list in Excel of all the records which have postcodes starting with: 1) B1 – B99 2) LE1 – LE67 3) CV1 – CV47 4) DE1 – DE99 5) NG1 – NG99

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    Hi, can you help me out to code Verilog coding for the sound detection sensor for turning on the LED on DE1 SoC Cyclone V board?

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    debug FPGA program - Cyclone Altera chip หมดเขตแล้ว left

    I have a board i need to fix for an equipment in my store. Looking for an FPGA expert that can debug the program files i got from the manufacturer. I was told this should be simple for someone that knows what they are doing.

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    fpga video processing pipeline. -- 2 หมดเขตแล้ว left

    ...filters (like hq2x) 4. output from scaler is passed through optional scaline generator, where scanline parameters are passed as input wires : scanline color, scanline thickness, scanline interval 5. output is overlayed by the bitmap OSD with the same resolution as output format Requirements : aside from the DDR memory interface, or PLL no vendor or encrypted IP blocks can be used, for example no Altera/Intel video pipeline. Everything must be in written verilog source code. Must include verilog testbench that will accept input picture(in any format) and produce resulting picture(in any format). suggested pipeline i/o ports: Sysclk, [23:0] RGBin, HSin,VSin,DEin, Clkin [23:0] RGBout, HSout, VSout, DEout, Clkout [31:0] parameters[0:...] (whatever count is required). all needed m...

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    NDA
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    1 คำเสนอราคา

    Alinhamento de fotos Criar botão de "ver mais" em texto home page criar botão "ver mais na descrição do produto e altera-lo de posição Banner de comunicado e menu moveis Seria estas as tarefas, é algo simples mas preciso com alguma urgência

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    Convert MATLAB code to VHDL code หมดเขตแล้ว left

    Need to Convert MATLAB code to VHDL code. I Have a MATLAB code i want someone who can convert that code to a sytnthesizable VHDL code for ALtera FPGA.

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    Envios em massa para Telegram หมดเขตแล้ว left

    ...faça todas essas funções abaixo. 1. Função de cadastrar contas .sessions na ferramenta. 2. Função que extraía os usuários de um grupo público no telegram que estejam com o status "Visto Recentemente" ou "Online". 3. Após Extrair os usuários do grupo do telegram cria um arquivo com todos esses usuários listados. 4. Analisa o arquivo dos usuários extraídos e inicia o envio de mensagens, e também altera de contas automaticamente quando bater certa quantidade de envios, além de ter a função Spintax, onde a ferramenta vai substituir uma palavra por outras automaticamente, por exemplo: Olá me chamo {Guilherme|Lucas|Pedro|Jo&...

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    FPGA Altera implementation หมดเขตแล้ว left

    Implement the circuit design in the FPGA, and read input /write output to the file. Including timing analysis, power consumption and pin planner etc... Using Quartus prime

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    To create user-level Linux programs that produce audio output on the DE1-SoC board. The task is to implement a digital piano that can play musical chords through the audio port of the board.I just want the code till part3 in the pdf which is present below. skeleton code for those and header files, address files also present in the design files

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    0 คำเสนอราคา

    Read the pdf. the 7 segment LEDS can be used to show the frequency. The main job is to build a NCO that creates frequency between 10 hz to 10 Mhz and then read it on a frequency meter with 1 Mhz clock and display the value on 4 digit 7 segement LED.

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    BPSK demodulation using fpga หมดเขตแล้ว left

    I m looking for a fpga design for an BPSK demodulator, the fpga ill be using is altera, i ll also require an simulink file illustrating the functionality of the demodulator, i provide the input file for the demodulator.

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    Write VHDL code and testbench for the given question and simulate them using Quartus and Modelsim Altera

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    Quartus ALTERA project หมดเขตแล้ว left

    Design a fully digital, hardware-based direction discrimination and counting system for use with quadrature encoder-based rotatory incremental encoders.

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    I need VHDL Designer หมดเขตแล้ว left

    This is a final year project. We are struck with simulation. Need to debug our program, or else develop the project from scratch. I am attaching the code that we have wrote for your reference. We used Quartus altera for coding, and model sim for simulation. The development board is a cyclone 2. There were no errors as such. The code would simulate and after one clock cycle, the output would become 'Z'. From what I understood, the main issue is the interconnection between all the modules.

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    Hello. I have a sales system (ERP) that has an open API. I need and a BOT/System that whenever a sale happens, the bot sends a message to my client via whatsapp. System API is very complete. The API notifies you when there is a sale, the API has all the customer's data such as Phone number, Name, Address, emai...thank you message, with order information (information is available in the API) Bot need use my own mobile number... Invoice API: Order API: Callback Status order: ( portuguese, translate to your language )

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    Altera De1 SoC FPGA หมดเขตแล้ว left

    Write a program using QUARTUS ALTERA to work on De1-SoC FPGA BOARD. .................. The LED Brightening Control with an Absolute Encoder The circuit to be designed must provide control of the brightness of a single or multiple LED ‘s using values from an Absolute Contacting Encoder (128 positions). In addition, the circuit must display a decimal value of the LED intensity (0-127) by using three seven-segment displays. The circuit contains four logic blocks and 3 external components (Figure 1). The logic circuits are: • Code Conversion Table • Binary to BCD 3 digits (Decimal Values) • LED Brightening Control (PWM) • Seven Segments Decoder

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    Traffic Control System หมดเขตแล้ว left

    Traffic Control System (Two intersection road) using VHDL in Quartus II. Write Code, test bench and simulate in Modelsim Altera. Draw Flow diagram or ASM chart and Mnemonic document state diagram.

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    In this project I want to see how the ADC works in FPGA kit .. with any sensor LED or temp. The board is ALTERA Cyclone IV EP4CE6e22cb

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    aplicativo energia solar หมดเขตแล้ว left

    preciso criar um aplicativo para conectar nos aparelhos solar para puxar o consumo do cliente ver detalhes quanto tempo gero energia , gráfico de produção de energia tem que ser dois app um para cliente visualizar quanto esta a produção e outro app para criar o acesso do cliente altera a senha do cliente e visualizar todos o cliente quanto estão consumido

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    Plugin Woocomerce de Tabela de Preço -- 2 หมดเขตแล้ว left

    ...estão no Woocommerce. Seria mais ou menos uma lista criada por blocos e linha, blocos seria para especificar manualmente uma categoria e na linha o nome do produto colocado manualmente e uma opção para procurar e selecionar o produto que ser vinculado a essa linha, uma vez vinculado vai aparecer na frente o preço e sua variável para ser selecionada caso tenha e uma vez alterado o preço ele também altera e salva no Woocommerce, nessa opção era bom ter um botão para salvar e excluir a linha. Uma vez a linha feita logo abaixo poderia ter o botão de mais para adicionar novas linhas ou blocos. Tudo isso feito é preciso gerar um shortcode ou algo do tipo para gerar um html e ser publicado em uma pagina...

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    Quartus Altera/INTEL หมดเขตแล้ว left

    Looking for a tutor on Quartus Altera/Intel MAX10 FPGA device. Knowledge of QSYS, Platform designer, Eclipse, HDL/VHDL. Embedded system control design using FPGA. Closed loop control ADC sampling, PI controller , PWM generation in HDL/VHDL.

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    Looking for website content for Power electronics converter for battery chargers for EV market. Magnetics design , Embedded software FPGA. Altera/Intel VHDL.

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    VHDL SD card implementation หมดเขตแล้ว left

    Hello, In my project I need to store data on my FPGA Altera EVMs. The data must be stored on a non-volatile device (power done can occur at all time). To do that, I need to implement an interface to the on board uSD card. Here are some specification: 1. SD Card: Class 10, 2GB. 2. Min write speed: 200Byte every 1ms (effective) ~1.6Mbps. 3. Read speed: 10Mbps (Flash all mode) 4. All VHDL (NiosII- only when guaranteed performance). 5. Full Duplex- Optional. 6. Target: DE10-Nano and DE2-115. 7. Delete all data function: optional. Thanks, Idan

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    resolver problemas de execução de sketchup หมดเขตแล้ว left

    Preciso de ajuda para poder trabalhar com meu programa, tenho placa de video geforce940mx configurações compativeis, e o programa trava muito, baixei um programa para fazer checkup dos requisitos e la diz que estou usando uma placa intel e que poderia melhorar usando a nvidea, mas faço a alteração nas definições da nvidia, e faco o checkup novamente mas nao altera.

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    FPGA I2C module หมดเขตแล้ว left

    prepare a I2C module for Altera FPGA

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    - A aplicação parou de funcionar devido a alteração de nomes de parâmetros do WhatsApp. - Necessário verificar quais parâmetros pararam de funcionar e altera-los de acordo com os atuais - Criar documentação técnica e funcional da aplicação já desenvolvida para melhorar o suporte. - Funcionalidade da aplicação: A aplicação já desenvolvida apenas exporta os números das conversas do whatsapp que não possuem na agenda (novos números)

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    VHDL simple set of PROJECTs to simulate หมดเขตแล้ว left

    VHDL , QUARTUS , MODELSIM ALTERA, QUESTASIM, UP DOWN COUNTER , COUNT ZERO COUNTER, CLOCK GENERATOR, RGB CONTROLLER. STATE MACHINE ...

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    INTERFACE a ADC with TERASIC DE4 board หมดเขตแล้ว left

    The AD 9254 is to be interfaced with TERASIC DE4(Altera startix IV) in DSP builder platform

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    Hi I need an expert in these two software Altera Quartus II Computer Aided Design Software and Modelsim-Altera Simulation Software. inbox me for more details.

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    1. Encode key presses on a standard 16-key 2. give a stable 4-bit binary output 3. Have output to indicate when a key is being pressed.

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    VHDL / FPGA Development หมดเขตแล้ว left

    to design and implement a game clock on the DE1-SoC development board, using any of its on-board resources (buttons, switches, seven segment displays etc.). The game clock should have two modes of operation to allow the following variations: • The first mode of operation should give each player a fixed amount of time for the whole game. There should be a suitable indication if either player runs out of time. • The second mode of operation should be a game clock variation of your choice. You should produce a report (maximum 1500 words, excluding appendices), in pdf format, that gives a comprehensive account of the design process including the hardware setup, VHDL code testing and evaluation. It should also include: • Instructions for the user. • The full set of...

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    7 คำเสนอราคา

    You are required to design and implement a game clock on the DE1-SoC development board, using any of its on-board resources (buttons, switches, seven segment displays etc.). The game clock should have two modes of operation to allow the following variations: • The first mode of operation should give each player a fixed amount of time for the whole game. There should be a suitable indication if either player runs out of time. • The second mode of operation should be a game clock variation of your choice. You are free to decide the user interface, but the following should be kept in mind: • A minimum of user interface hardware (such as buttons) should be used. • The user interface should be as easy and intuitive as possible. • The VHDL design should use the...

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    DDR3 layout in Altium หมดเขตแล้ว left

    Dissolve DDR3, FlyBy topology, 2 Altera SoC chips. 8 layers (S-P-P-S-S-P-P-S), 3 (4, 5, 8 layers) available for DDR wiring. Changing the placement of components is acceptable if critical. Alignment rules and signal classes are defined. Deadline until 28.02. It is possible to expand the order to a complete layout of the board with an increase in cost and extension of terms.

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    ปิดผนึก
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    Разводка DDR3 в Альтиуме หมดเขตแล้ว left

    Развести DDR3, топология FlyBy, 2 чипа Altera SoC. 8 слоев (S-P-P-S-S-P-P-S), для разводки DDR доступно 3 (4, 5, 8 слои). Допустимо изменение размещения компонентов, если критично. Правила по выравниванию и классы сигналов заданы. Срок до 28.02. Возможно расширение заказа до полной разводки платы с увеличением стоимости и расширением сроков.

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    Tampermonkey - Script jogo Browser หมดเขตแล้ว left

    Preciso traduzir o script é altera algumas ações de acordo com minha necessidade tbm quero mudar sua interface para diminuir a poluição visual! Aceito dicas!! Então preciso das seguintes alterações: Traduzir todo código é nomes para português Mudar a interface "Painel" para diminuir a poluição visual é facilitar o uso! Corrigir algumas funções existente é tira os erros é má funcionamento. Tudo que precisa ser feito esta descrito abaixo: Adicionar as seguintes funções; 1) Compras Joias no leilão quando atingir certa quantidade na mão! 2) Compra merc Leilão quando tiver (X) valor em atributo (X) 3) Ven...

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    Embedded Programming หมดเขตแล้ว left

    We are looking for a developer who has experiance in Embedded Application Programming. Typical Operating Systems Embedded Linux Android FreeRTOS μC/OS ARM, MIPS, Motorola, ST, TI, Microchip... Arduino Xilinx MicroBlaze (Softcore Processor) Xilinx and Altera FPGA (see Electronics Overview) Identifying and removing bottlenecks with performance analysis and tracing tools. Using low-level languages such as C or assembler for greater control over resource usage. Developing unit tests to quickly verify software modules on higher performance machines. Tuning code for low memory usage and looking for memory leaks using tools such as Valgrind. Preventing memory leakage by using static allocation if necessary (for example in a safety critical application). can develop user interfaces...

    $250 - $750
    ปิดผนึก NDA
    $250 - $750
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    Electrical Engineering/Altera Quartus/Logic Design หมดเขตแล้ว left

    I need guidance with Altera Quartus and introductory Logic Design/Electrical Engineering work.

    $108 (Avg Bid)
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