c Integrated Circuit (ASIC) implementation of an N x
N array multiplier. The ASIC will be fabricated in AMI 0.5 m CMOS technology available through
MOSIS.
I have been designing such kind of projects since 2015. I have experience on 32nm,45nm,65nm,90nm and 180nm. designed on tanner eda tool and cadence tool. Also hands on ADS software
I can design your multiplier within a week if required on 28 nm technology as I don't have AMI access.
Relevant Skills and Experience
I have hands on practice on cadence virtuoso 28 nm technology