Building simulation design for CMOS low dropout regulator that can address PSR in Cadence virtuoso environment by using TSMC40nm design tools.
Requirements:
Familiar with software and design tools
Simulation results, charts and graphs
Results analysis
To be complete by29august
Hi there,
please leave a message on my chat so we can discuss the budget and deadline of the project. I have read your project description and i'm confident i can do this project for you perfectly. Thanks
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Dear client, I read about your project and I can do it for you, I'm microelectronics engineer and I used virtuoso many times throughout my projects. contact me because I've some questions and concerns to ask about.