Xilinx Vivado project ref. design

Dear Sir. I am interested in your project and I would be happy to work on it. I can make the design and finally synthesis to a .bit file. I am a Senior Electronic Engineer with experience in the design / development of embedded systems implemented with DSP, FPGA and Microcontrollers. In my 6+ years of experience in the Aerospace and IoT industries, I worked in electronic/circuit design, PCB layout, embedded C programming and digital design. In my experience in the aerospace area, I worked in high-speed designs on FPGAs using VHDL. I have the skill to solve problems, the rapid understanding of what is required, seriousness and responsibility to carry out the work in the best way. I am new to the freelance platform, but I am sure that I am the professional who can do this job. You can trust that I will give my best to deliver a work that exceeds your expectations. Thanks for your consideration Best regards

Hi, I hope you are doing well and enjoying digital design. I believe implementing a design right form modeling until verifying it on an FPGA is always a very special experience. Throughout my 2+ years of experience in the field, I had the joy of designing and implementing a part of LTE's physical layer right from the Matlab model, through RTL coding, simulations, and back-end stages. I also built many other designs such as a MIPS processor design, Can satellite, and a UART transmitter and receiver. All my designs were verified successfully on either Xilinx's Spartan S6, S3, or Altera's Cyclone V FPGA. The process of building some RTL design differs according to the final destination of the project. For instance, a design for ASIC tape-out will have other methodologies of debugging and verification than if it's for FPGA. Subsequently, I would like to know which methodology of testing you would prefer me to adopt, simulations or UVM environments. It is up to you really. I am fine with both. I would love to hear your thoughts and requirements for the delivery as well. I wish you get the best out of this project. - Eslam

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I have been working on vivado block designs , I'm quite familiar with tool flow and viavado 2018.1. I can make this faster if you assign it to myself..I can give you all the screen shots and results.. Relevant Skills and Experience Verilog, Fpga Xilinx, Intel . Vivado 2018.2 Zynq cvgt fpga

J'ai besoin de plus de détails pour pouvoir vraiment décider. ....................................................................................................

I working on Vivado 2018.2 but ready to help you! I have worked on designing various IP cores. Worked on emmc controller, DMA engine, regex IP core, CSI controller, etc.