I can send all the details upon request.. looking for VHDL expert to handle a task
sign meets the specifications; d) report about your design.
You are required to design code for your target hardware (a Digilent Basys3 board with a Xilinx
Artix 7 FPGA) in order to implement a design that meets the specifications (below). You are
required to submit working and correct code and you are strongly encouraged to use a modular
coding style (allowing for greater flexibility, maintainability, modularity, and reusability). To show
that you master all aspects of the language, your code should prevalently use concurrent statements
for combinatorial circuits and sequential code for sequential circuits. Additionally, the use of nonstandard
packages (e.g. STD_LOGIC_ARITH, STD_LOGIC_UNSIGNED, STD_LOGIC_SIGNED) and BUFFER
ports is forbidden, while the use of INOUT ports is accepted only when strictly necessary
Hi,
-FPGA design engineer since last 7 years
-Expertise in verilog/VHDL
Please find below details of the projects
TSMAC Hardware acceleration(3months)
The project is to develop hardware acceleration block for TSMAC IP to reduce the overhead created in software for packet creation and detetction.
CSI-2 transmitter and receiver(6months)
The project is to develop CSI-2 transmitter and receiver IPs according to the mipi standards
eMMC Host Controller and Device controller(3months)
The project is to develop eMMC host and Device controller IP according to the JEDEC standards.
Mobile camera–testing(3months)
The project is to develop 3D image processing algorithms on 1K sensor from PMD technologies
High resolution camera(6.5months)
The project is to develop 2D and 3D image processing algorithms on 100K sensor from Infineon sensor
-Test project for DDR2 accesses
-Development of calibration module
-Development of chain control module
-Development of control signal generator
-Development of Generic LUT module
-Development of Divider radix-2 algorithm
-Development of atan calculator
-Development of MCB reader state machine
Color Pipeline(15months)
The project is to develop 2D and 3D image processing algorithms on Aptina sensor
-Development of Generic Frame Buffer pCore
-Development of data compression and data packing pCore
-Development of data packing pCore
Video Processing Unit(13 months)
-Improvement in algorithms to reduce FPGA resource utilization and decrease latency
I’m an innovative design engineer with 5 years of experience design, develop and verify products and processes. I have spent the last five years developing my skills as FPGA and embedded system developer, with learning HDL languages like Verilog VHDL and embedded C. In these years, I have complete several small and big projects like developing an interfacing protocol to NADN Flash. I love designing and solving problems
I've more than 10 year experience in Memory Controller designing on Xilinx FPGA devices. Clear knowledge about Xilinx FPGA architectures. Expertise in VHDL/Verilog