Help me to fix my ADC in VLSI project

I am an Analog/Mixed-signal Design Engineer with over than 7 years of industrial experience in CMOS IC Design. Participated in over 10 projects with high volume productions. Experienced in complete product development from initial conception through design, verification, fabrication & testing. Extensive experience of working with different teams across the world (Canada, Europe, Egypt, Macau, India). TECHNICAL SKILLS: • Analog/mixed-signal engineer with a primary focus on the design of high-speed serial interfaces (HSIC, USB 2.0, USB 3.0). • Transistor level design and layout supervision of analog building blocks (SERDES, PLL, High-Speed TX/RX, Crystal Oscillators, full on-chip Precision Current/Voltage References, Multipliers, Opamps, Comparators, Level-Shifters, Voltage Regulators, I/O.). • Experience in deep submicron planar CMOS (from 90nm down to 20nm) and FinFet (16nm, 10nm, 7nm) analog design for the most fabs and processes.

hi, I do work in Cadence Virtuoso. I do have Cadencee 6.1.6 and also 6.1.4....hope I can solve your issue regarding ADC ckt design and simulation in ADE waiting for your response