verilog assignment
$30-250 USD
ชำระเงินเมื่อจัดส่ง
Hello, i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions.
Some is the work that I have done so far. I am currently working on the execute part and it only works for 101 cycles and not 4000 as instructed in the video.
Have to finish this four parts
Fetch
Decode
Execute
Writeback
Using my execute code, I am stuck on the execute part as it only performs 101 cycles and not 4000.
Contact me for documents
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freelancer 10 คน กำลังเสนอราคาในงานนี้ โดยมีราคาเฉลี่ยอยู่ที่ $127
Dear sir I have more than 10 years experience in digital design using verilog, please check my profile also please message me so that we can discuss Best regards
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I have already done some RISC projects before. I will finish your project on time. Please award it for me.
Hello, I am working in the ASIC design flow for 10 years. I have experience in using VCS FOR SIMULATION, DC for synthesis and ICC for layout. I have just completed the RTL and Testbench code for design multi core chip เพิ่มเติม
I am professional FPGA programmer with over 10 years of experience in processor logic design and development.