Hi there!
I'm based in Ahmedabad, India. This project is related to lightweight cipher, cryptography. I have attached a pdf containing information relevant to this project which can be found in section 3.1 of uploaded pdf (round-based based architecture of PRESENT-80).
The code has already been developed and I'm getting the proper results as well. But I want to build a clock based design so that I can perform power analysis on it. Need the code properly working in two days.
I looking for a Clock based implementation on existing design
Language used : VHDL
Hi,
I am good in VHDL and Verilog. I implemented ip core of floating multiplication, FIR filter in HDL. I am extensive experience in ISE, Vivado of Xilinx and Quartus of Altera.
I believe I am the best person for this project.
Regards,
Chhanda
Hello My friend,
I Ahmed Zaky, Senior Nanoelectronics Engineer. I have worked with PRESENT algorithm before and I know how it works very well. I can help you with making both the encryption and decryption in Verilog not VHDL if this suits you. I guarantee 100% mistake free synthesizable code and on time delivery.
Looking forward to hearing from you.