Multiplier Cell Desigen for Multiple Applications

I have already worked in the Multiplier design using FPGA. You can verify it in the google through the title '''FPGA Implementation of 8-bit Multiplier with Reduced Delay Time' Relevant Skills and Experience Ability to develop VerilogHDL for specific applications. Proposed Milestones RM11 MYR - Understand the concept RM70 MYR - Prepare the documentation RM20 MYR - Verify that the documentation is correct

I have well experienced in doing such kind of jobs......................... Relevant Skills and Experience VLSI, Proposed Milestones RM66 MYR - i will do my level best