I need someone who knows MIPS Assembly Language and knows how to use the LogicWorks software to design a Single-cycle processor (see Figure 1 in attached document) and a Five-stage pipelined processor (see Figure 2 in attached document). Please keep all bids within the budget, otherwise you will not be selected for the project.
I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I have done the work before
Relevant Skills and Experience
FPGA/VHDL/Verilog
Proposed Milestones
$150 USD - the whole work
I have similar project already done so have the ready cde with me .
I can deliver it in 48 hrs
Relevant Skills and Experience
Experienced FPGA design engineer since last 7 years and have both VHDL and verilog coding hadson
Proposed Milestones
$111 USD - Milestone
i have already done this work of designing MIPS processor
Relevant Skills and Experience
I have designed MIPS processor
Proposed Milestones
$100 USD - UART design
Stay tuned, I'm still working on this proposal.