Investigating Hardware Debugging Assistance

We are a research group at the University of Michigan working human study involving debugging assistance for Verilog designs. The study involves asking designers to debug mistakes in circuit descriptions, either with or without some form of debugging assistance. The debugging hints can take the form of highlighting the wire or register name with the bug, or highlighting several lines of code likely containing the bug. We are hoping to figure out what forms of debugging assistance work best in helping hardware designers fix mistakes efficiently, and eventually hope to integrate our findings into a learning tool aimed at teaching novices how to write Verilog descriptions. The study is expected to take around 45 minutes to an hour to complete, and we will compensate people familiar with Verilog $25 for one hour of their time.