need to implement an ieee paper using verilog or vhdl.

Dear sir I have more than 10 years experience in digital design using fpga, please check your profile also please message me

Dear Sir/Madam, I have about 7 years experience in verilog and system verilog languages. I keenly want to work on this project. I assure to finish the project within 15 days. Thanks, Punam

I have done many IEEE projects during my college day. I could help you out in that way. Lets work cool bro..