Recursive karatsuba multiplier (16bit)

A proposal has not yet been provided

I have proficiency with VHDL and Verilog. I am good with Xilinx and Altera FPGA. Are you referring any IEEE paper

I have more than 10 years of an experience in the FPGA/ASIC design and also I have an experience in the implementation of a mathematical algorithms.

Hello, This is a rather tricky project, so I raised the reward. Any particular reason for that algorithm on just a 16bit signed integer? But anyway as a Verilog HDL programmer and one who knows the algorithm, I can เพิ่มเติม