Micheal S.

I am a passionate electronics engineer who likes to learn and explore complex designs/systems, I like to improve my skills through challenging problems and new opportunities in the field of VLSI. I gained knowledge from my academic study and technical knowledge from my trainings and graduation project with Siemens EDA. I seek more knowledge from more projects to sharpen my skills whether in digital IC design or verification. Skills: -RTL using Verilog and VHDL. -Verification using SystemVerilog, UVM, PyUVM(UVM using Python). - Experience with tools like Modelsim, Xilinx ISE Design Suite and Synopsys Design Compiler. - Scripting using TCL -Knowledgeable of Design Methodologies like Power-Aware Design, CDC & DFT. -Knowledgeable of Back-End flow like Clock Tree Synthesis, Placement & Routing.