Pruthvi R.

Thank you for viewing my profile. I have total 12 years experience. mainly worked on Micro architecture and coding. Validation. TCL/Perl scripting programming languages; 1. Veriog, VHDL FPGA : 1. project with high speed ADC and DDR3 memories on AXI, SRIO protocols and implementation in Xilinx and synplify tools ASIC: APB, AXi and Memory controllers(Flash) I2C and Quad spi designs Lint and CDC Synthesys using design compiler TOOLS 1. Xilinx Vivado/Xilinx ISE/IP Core of Xilinx. 2. Design compiler 3.Cadence vcs, simvision