Asic fpga vhdlงาน

I'm looking for an experienced engineer to reprogram my Intel Cyclone V FPGA with existing code to enable it to perform signal processing functions. The code itself is already written and I'd like the engineer to take that code and use it to program my FPGA. This project requires an in-depth knowledge of FPGA technology and experience with the reprogramming process. I'm confident that the right person can complete this task effectively and efficiently. If you believe you are up to the challenge, I would love to hear from you and discuss the details of the project.

I am looking for someone with a programmer to program an Actel APA300PQ208I FPGA. I have the program but do not have the required programmer. If you have the correct programmer and are familiar with this device, I look forward to viewing your proposal.

High performance Digital Filter design . 1. VLSI implementation of Filter architecture. 2. Implementation of Filter architecture for all DSP functions on FPGA 3. Enhance the speed of Filter architecture using different technique and implementation on FPGA. 4 Reduce complexity, area, power consumption of filter architecture and implement on FPGA. 5 Minimum utilization of Look up Table, Flip Flops, slices etc for FPGA design of filter. 6) IP diagram 7) RTL design & Wave form for same 8) Fault Findings ( if possible and if any ) 9) If any other parameters which you can add to demonstrate results

I am looking to hire a freelancer to design an FPGA function generator using a Altera MAX 10 FPGA, 10M08SAE144C8G that produces a frequency of 10 MHz and above. The desired waveforms are sine, square, and triangle. This function generator should also have a single channel. If you think you have the skills to help me with this project, feel free to bid on it. Thank you!

I need help with the implementation of SHA 512 on an FPGA platform. I prefer to use the Xilinx platform, and I would like the programming language to be Verilog. I need the project to be completed in 2-3 days. I know this is a short timeline but I'm confident that with the right expert, it can be done. Please let me know if you have any questions or require more information.

ASIC design Laboratory basic concepts. Place bid if you can start now.

For this project, am looking to create a system design for the game Beer-Pong using a combination of BASYS 3 and additional components compatible with BASYS 3 and VHDL. I want the system design to have a basic level of complexity with a specified deadline of 3 weeks for completion. Different components like switches, LEDs and sensors. The aim of this project is to design a system for the game Beer-Pong using BASYS 3 and components that are compatible with BASYS 3. In this project, we will be able to play advanced beer- pong. Our setup will consist of 6 cups in total, and the aim is to throw three balls out of 5 into adjacent 3 cups Balls must perform a straight line). Thus, at that point, our game differs from the classical game. Positions of the cups can be adjusted since the playe...

...assist me with an Axi Ethernet 1G base project for Xilinx KCU116, which is a Kintex Ultrascale. Project MUST NOT CONTAIN Microblaze, only soldi VHDL code. Target Device: Target device is Kintex Ultrascale+, as KCU116 board will be the target device for the project. Intended Functionality: The main objective of this project is to develop a networking solution using Ethernet. The freelancer should be experienced in VHDL developments and in networking functionalities for Xilinx KCU116. Specific Requirements: - 1/2.5GB Axi Ethernet Core (not provided, but free trial is available by Xilinx) based - 1Gb speed required - No Microblaze or MPSoC, only VHDL code. - Configuration must be done by AXI-Lite bus (No Configuration vector) - Ethernet frames must be sent by AXI-St...

For this project, I am looking to create a system design for the game Beer-Pong using a combination of BASYS 3 and additional components compatible with BASYS 3 and VHDL. I want the system design to have a basic level of complexity with a specified deadline of 3 weeks for completion. Different components like switches, LEDs and sensors. The aim of this project is to design a system for the game Beer-Pong using BASYS 3 and components that are compatible with BASYS 3. In this project, we will be able to play advanced beer- pong. Our setup will consist of 6 cups in total, and the aim is to throw three balls out of 5 into adjacent 3 cups ( Balls must perform a straight line). Thus, at that point, our game differs from the classical game. Positions of the cups can be adjusted since...

...and Simbl Pty Ltd Registered (2) DEC 2021 – Provisional Blockchain Patent Filed for Recycling (3) JAN 2022 – Global Patent Novelty Search Initiated (4) FEB 2022 – First Simbl Recycling White Paper Drafted (5) MAR 2022 – 18 Novel Claims Awarded to Simbl Provisional Patent (6) APR 2022 – Domain Secured (7) APR 2022 – Simbl engaged the Australian Securities and Investment Commission (ASIC) Innovation Hub (8) MAY 2022 – Product refinement and Non-Technical Light Paper Drafted (9) JUL 2022 – First App Prototype UX Built (10) AUG 2022 – Team Building – Independent Blockchain Developer and Advisor Selected (11) SEP 2022 – Advisory Team Formed (12) OCT NOV 2022 – A+B Testing of Product and Concept (13) DEC 2022 &nda...

Create a simple yet effective Smart Home Energy Monitor using your expertise in electrical engineering and FPGA/VHDL. This project aims to help working individuals monitor and optimize their home energy consumption. It can be both fun and practical.

...ASR 1004 rp2 Software and Romon,cpld,fpga Update Description: I am looking for a skilled professional who can assist me in updating the software and components of my Cisco ASR 1004 rp2 device. The main focus of this project is to update the software, Romon, cpld, and fpga. Current Software Version: I am not sure, please check for me. Specific Features/Fixes: I am not sure, please recommend. I am open to suggestions on the latest version and any specific features or fixes that would enhance the performance and functionality of my device. Backup: Yes, I have a backup of my current configuration and data. Ideal Skills and Experience: - Strong knowledge and experience with Cisco ASR 1004 rp2 devices - Expertise in updating software, Romon, cpld, and fpga componen...

I am looking for a skilled FPGA designer with experience in Xilinx Zynq7010 EBAZ Verilog to develop a permutation enumeration counter. The counter should have the following functionality and requirements: Functionality: - The counter should be able to increment indefinitely. - The counter shall initialize to the starting position on reset. - The counter shall toggle a minimum number of bits, like Grey Code. Requirements: - The project should be implemented using Verilog for Xilinx Zynq7010 EBAZ board. The Verilog function shall be parameterized PermCtr(K, N) - The counter should be designed to efficiently handle permutation enumeration. - The design should be optimized for performance and resource utilization. - If possible, I would like the counter to only enumerate the space be...

We are currectly looking for support to write a simple motor model in VHDL, that will be used to test our motor controller in FPGA. The motor model shall be as simple as possible and an equivalent Matlab/Octave/Python/C/C++ model would be desiderable and used to validate the VHDL model

Project Title: Accelerometer control Platform: FPGA Skills and Experience: - Proficiency in working with FPGA platforms - Strong understanding of accelerometer technology and control - Previous experience in developing projects using accelerometers Project Requirements: - Develop an accelerometer control system using an FPGA platform - The main function of the system should be orientation detection - Successful freelancers should include their past work showcasing their experience in working with accelerometers - Detailed project proposals are not necessary, but a clear understanding of the project requirements and the ability to meet deadlines is crucial Deliverables: - A fully functional accelerometer control system that accurately detects orientation - Documenta...

requiring the design of a VHDL synthesizable module to interface an incremental encoder. This is generic ABZ quadrature decoder, some code woulc also be found on the net already, that requires integration and testing () The encoder is the Z is for homing (it marks the zero position of the encoder) specs and deliverables in the attached document

I am looking for a skilled freelancer to implement the JESD protocol on an FPGA device. The desired data rate for the implementation is 1 Gbps. Skills and Experience: - Experience in implementing the JESD protocol - Proficiency in FPGA development - Knowledge of high-speed data transfer and communication protocols Project Timeline: - The deadline for this project is within 1-2 weeks. Please provide examples of previous work and relevant experience when submitting your proposal.

I am looking to write and read memory from an EEPROM with a FPGA. The desired size for the EEPROM is 32kb and I need to use I2C as the communication protocol. I have a specified model for the FPGA, Cyclone IV. The project should also include the development of software code for the FPGA to control the EEPROM operations.

I am in need of an expert with FPGA Verilog/VHDL experience in Xilinx. The project requires advanced programming skills in Verilog/VHDL and must be completed within a week. You should have a Xilinx board to work on this project. Tasks: - Programming in Verilog/VHDL Ideal Skills and Experience: - Expertise in FPGA Verilog/VHDL - Strong knowledge of Xilinx - Advanced programming skills in Verilog/VHDL Deadline: - Within a week

I am looking for experts in Xilinx VHDL to be a part of my team and work with me on various projects. I need dedicated experts who can work in tight deadlines too I would encourage new freelancers too to place bid and have a communication with me

I am looking for experts in Xilinx VHDL to be a part of my team and work with me on various projects. I need dedicated experts who can work in tight deadlines too I would encourage new freelancers too to place bid and have a communication with me

I am looking for a freelancer who can develop a VHDL test pattern generator with the following requirements: Configurable output order configurable pattern configurable pixel per clock test in simulation only

We need asic engineer if you to work with us then mail us on [Removed by Freelancer.com Admin]

hi, i'm searching for an experienced in Matlab and VHDL i have a code written in matlab and it's calling some functions that also written in matlab and i want to convert the code into VHDL if you can convert it please bid on this project

I have an FPGA carrier board and I am interested in someone to review it and make any suggestions for improvement. This is a carrier board for an Alinx FPGA core board. It is basically a version of Alinx's carrier board with all the parts I don't need removed. The board has 10G Ethernet via an SFP, Gigabit copper Ethernet, USB 2.0, and a few minor things. I developed this board because I need to generate the SFP clock differently, and the off-the-shelf board cannot accommodate the change. I stuck closely to Alinx's design for maximum compatibility with our current usage of the Alinx board, so this request concerns not the parts but the PCB layout. It is a 4-layer design in KiCad. I tried to take care with impedance and layout, but a more experience set of eyes...

Hello I have a project written in Matlab, I need to convert this code to VHDL by using Vivado.

I am looking for an experienced crypto mining tech to help me with a project for mining Bitcoin. I have specific hardware requirements, which include ASIC Miners. Therefore, I need someone experienced in working with this type of equipment and familiar with the best practices for maximizing the mining potential of such hardware. The successful applicant should be able to demonstrate a deep understanding of crypto mining techniques, be able to manage specialized mining operations, and possess the necessary skill to drive the project to successful completion. My goals are to maximize the hardware potential, minimize the costs associated with the mining process, and optimize the returns. In addition, I am open to hearing advice and suggestions from the successful candidate on how we c...

I am seeking an experienced professional to help with a project involving Xilinx FPGA development. I am using the Xilinx Zynq-7000 board and the main function of the board in my project is to process data. I need help with both hardware design and software development for this project. The qualified candidate should have significant expertise in hardware design and software development for FPGA systems. Excellent knowledge of C/C++ and VHDL for FPGA design/programming is also necessary. The candidate should be able to understand and utilize various types of FPGA peripherals and interfaces including, but not limited to, SPI, I2C, UART and Ethernet. Working knowledge of the Zynq-7000 series FPGA board and its associated software/tools (e.g. the Xilin...

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I want to implement the Ethernet connection between FPGA board to PC. The deliverables are as follows - Verilog code to run on a Spartan 6 Board - (xc6slx100) - Simulation time diagrams (more details will be given to the winner) - The code should be able to transmit and receive data at 1000mbs.

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I am looking for a skilled freelancer who can apply clock gating techniques to my ASIC design. The project requirements are as follows: Intended Application: - The ASIC design will be used for encryption purposes. Ideal Skills and Experience: - Strong knowledge and experience in ASIC design and clock gating techniques. - Proficiency in working with clock gating tools and methodologies. - Familiarity with low power design techniques and power optimization. - Experience in encryption or AES

- A report of minimum 6 double-column pages for the case study It should follow the IEEE Template (). - Select a research problem in FPGA - Do a literature review. - Perform implementation of at least one paper (if any) - Discuss the available solutions to the problem - Propose a novel solution to the problem (if any)

I am looking for a freelancer who has extensive knowledge of ASIC chips and their architecture, specifically in the context of firewalls. Main Goal: The main goal of this project is to understand the architecture of ASIC chips in firewalls. Timeline: The preferred timeline for completing this project is today. Skills and Experience: Ideal candidates for this project should have: - Extensive knowledge of ASIC chips and their architecture - Experience in working with firewalls

I am looking for an experienced VHDL programmer to help with a complex project. The timeline for this project is within a week, so it will require an experienced programmer who is able to work very quickly. I have detailed requirements that need to be satisfied, and I will be expecting a high-quality result. The project is an advanced level project, so I need someone who is comfortable working with complex VHDL code. If you think you can complete this project in the timeline given, please message me!

Project Description: Can you help me with a mini spectrum analyzer using FPGA the results will be on a pc screen with GUI that the user can put markers on and change the resolution, to make a spectrum analyzer with FFT algorithm on FPGA Using UI the user can control the span a put markers. The user will be able to change parameters in a user interface. The ADC is the sampling. The FPGA is going to calculate the FFT. The all idea is to mini spectrum analyzer (the measurement device). Block chain 1. ADC for sampling 2. FPGA to calculate the FFT and sent it to the pc display

Project Title: FPGA Xilinx Spartan 7 for Digital Signal Processing Application Skills and Experience: - Proficiency in FPGA development using Xilinx Spartan 7 - Strong background in digital signal processing - Experience in writing HDL code from scratch - Familiarity with FPGA design tools and methodologies Project Description: We are looking for a skilled FPGA developer with expertise in Xilinx Spartan 7 to assist us with a digital signal processing project. The main application of the FPGA will be digital signal processing, specifically in the area of [insert specific application]. Requirements: - Develop FPGA design using Xilinx Spartan 7 for digital signal processing application - Write HDL code from scratch based on project requirements - I...

I am looking for a freelancer to help with hardware verification. Specifically, I would like someone to verify a VHDL model od SHA3 in SystemVerilog using the UVM (Universal Verification Methodology). This project will also require executing fewer than 10 verification test cases. I have semi-built UVM template to send.

My experience with deploying Caffe networks on FPGA boards is intermediate. I have prior experience with the Lattice Radiant software so I am ready to use it for this project. My specific task or outcome I want to achieve with this deployment is Image Classification using the ICE40UP5K FPGA with the iCE40 UltraPlus Breakout Board and Lattice Radiant software.

My experience with deploying Caffe networks on FPGA boards is intermediate. I have prior experience with the Lattice Radiant software so I am ready to use it for this project. My specific task or outcome I want to achieve with this deployment is Image Classification using the ICE40UP5K FPGA with the iCE40 UltraPlus Breakout Board and Lattice Radiant software. Details: 1, I already built a caffe network, just need to deploy it 2, the input of the caffe network is supposed to be an image but right now the input of the caffe network are 32x32 matrix and output will be 1 or 0. I want to test that with deploy the model on ICE40UP5K 3, I will provide the network file, and the final result will be a project file and can use my caffe network, have hardcode a 32x32 matrix and output ...

My project is about FPGA programming for control systems. I'm using the Altera Cyclone V board and the preferred programming language is Verilog. This project requires someone with experience in FPGA programming and the design of embedded systems. The programmer should be able to develop design flows for FPGA devices, debug them and modify existing designs for better performance. The knowledge of hardware description languages such as VHDL and Verilog is crucial, as they will be used for implementation and testing of the designs. Additionally, some knowledge of microcontrollers and communication protocols will be required. The right person for this job should have strong problem-solving skills, excellent coding and debugging capabilities, and a deep underst...

I am in need of an experienced and professional digital circuit designer to undertake a project involving Verilog coding, RTL verification, and FPGA implementation. Specifically, I need the Verilog coding to be at the intermediate level and it must meet specific requirements. The scope of this project is just Verilog coding running though Xilinx Vivado IDE. The successful applicant must have a good understanding of design flows to be implemented in Verilog, including synthesis and simulation techniques, as well as a thorough knowledge of all aspects of Verilog coding and digital circuit design. Experience with RTL verification and FPGA implementation will also be beneficial for this role. Ultimately, I am seeking an individual who is able to accurately analyze the specificati...

Project Title: Altera DE0 Board Programming Assistance Description: I am seeking a freelancer who can provide programming assistance for my Altera DE0 board project. I require expertise in VHDL programming language and the ability to modify existing code as well as start from scratch. Skills and Experience: The ideal candidate for this project should have: - Proficiency in VHDL programming language - Experience with Altera DE0 board - Strong troubleshooting and debugging skills - Knowledge of hardware design consultation Specific requirements: - Provide programming assistance for the Altera DE0 board - Modify existing code and develop new code from scratch - Troubleshoot and debug any issues that arise during the programming process - Provide hardware design consultation a...

I am looking for a skilled programmer to work on the video processing project involving the GS2962 and GS2961 ICs. Programming Language: - Proficiency in VHDL programming language is required for the IC programming. Functionality: - The primary function of the programmed ICs should be video processing. Hardware Compatibility: - The IC programming should be compatible with specific hardware that I have specified. Ideal Skills and Experience: - Strong knowledge and experience in programming with VHDL language. - Expertise in video processing and working with ICs. - Familiarity with GS2962 and GS2961 ICs. - Ability to ensure compatibility with specified hardware. Please provide examples of previous projects related to video processing and IC programming when submittin...

I am looking for someone to help me with the installation and setup of the Ironfish miner on my Windows operating system. I will use FPGA or GPU solution of teamredminer. As a beginner in cryptocurrency mining, I am in need of assistance from someone with experience in this field. Some of the skills and experience ideal for this job include: - Proficiency in installing and setting up mining software - Knowledge of the Ironfish miner and its specific requirements - Understanding of Windows operating system and its compatibility with mining software - Patience and ability to explain the process to a beginner in a clear and concise manner - Troubleshooting and debugging skills to address any issues that may arise during the installation and setup process If you have previous experien...

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We are searching for support on debug test and addition of a couple of features to a project we developed last year The board is a synchronous (with GPS PPS signal) acquisition from 7 ADCs. The clock is generated internally from a PLL, locked to the PPS. Lattice ECP5 on a custom board There are 2 external interfaces to an IMx6 SPIM: Spi Slave, the Master is a Imx6 processor, which is used to write and read internal registers and ADC’s registers. Details on the protocol in the FDD SPIS: Si Master, the data acquired from the ADCs are packed and sent to the external IMx6 Modifications ADD MEMS Accelerometer, ADXL355 channel modify the data stream, adding 8th channel. A review of protocol might be needed ADD Registers to control DAC and discretes ADD DAC. We can share a DDS to generate ...

I am looking for a skilled ARM embedded freelancer to assist with ...of the Embedded System: - Personal project Hardware and Software Requirements: - I have specific requirements Ideal Skills and Experience: • Good grasp of fundamentals in Electronics Engineering, • Knowledge of digital electronics, VLSI, microprocessor architecture is a plus • Interest and experience in digital design and verification • Good understanding of Assembly-level programming, Verilog/VHDL • Proficient in C/C++, and scripting languages - Strong knowledge and experience in ARM microcontroller programming - Proficiency in real-time operating system (RTOS) development - Expertise in embedded system design and implementation - Familiarity with the specific hardware and software req...

We are currently running 4 Asic miners and i want to envelope a way for users to log onto the app and essentially help with the pricing of mining by being able to but around 1/4th of each miners ability to aid in the development of more machines so that i can help cover the costs of the mining operation growning.

I am looking for a skilled VS code extension developer who can create a language support extension for VHDL/Tcl. The ideal candidate should have experience in developing VS code extensions and have a strong understanding of external tasks. Requirements: - Proficiency in developing VS code extensions - Familiarity with the VS code extension development process - Ability to create a language support extension We have a language support extension already, that support VHDL and Tcl programming language. we need support to add tasks to the extension, to call external scripts. more details in following communications