embedded s

Project: The project consists of multiple phases. It is to develop a logic analyzer and waveform viewer (LA/WV) that can send data to a PC for display. The data collection is done on the FPGA board. A microprocessor gets data from the FPGA board and sends data to the PC through either a Bluetooth modem or a USB port. The system supports one analog channel and one digital channel, with a single-level triggering. Only 8 bits of precision will be used for the analog channel. •Phase 1: Develop a minimal system that contains a PC, a microprocessor board, and an FPGA board. With this system, a PC application allows a user to “awaken” (or “start up”) the FPGA board through the microprocessor board. Once (and only after) the FPGA board is awakened, it waits for a push button action. After the button is pushed, it sends an 8-bit value in bit-serial to the microprocessor. The microprocessor then sends a sequence of corresponding characters (one or zero) to the PC application which displays the character sequence. You may use Termite as the PC application in this phase, but not in later phases. •Phase 2: Add two-way communication and graphic display to the minimal system. With this system, a PC application allows a user to awaken the UNO board by sending an 8-bit unsigned integer, denoted as THRESHOLD, to the FPGA through UNO. Once (and only after) the UNO board is awakened, the UNO board waits for 100 samples from the FPGA board. The FPGA board again waits for a push button action. After the button is pushed, it performs XOR operations on the 8 THRESHOLD bits. Depending on whether the XOR result is one or zero, it sends back the 100 8-bit count values of either an up counter or a down counter. Communication between UNO and FPGA should be done in a bit-serial fashion